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11
FN9186.3
January 3, 2006
The two channels can be forced to track each other by
simply tying their SS pins together and using a common SS
capacitor. In addition, their EN
 pins also must be tied
together. Typical Start-up waveforms in this mode are shown
in Figure 15. If one channel goes down for any reason, the
other one will too. One important thing to note here is that
only the overcurrent latch-off mode will work. Auto-retry
feature WILL NOT work. Retry must be controlled manually
through EN
.
Typical Hot-plug Power Up Sequence
1. When power is applied to the IC on the BIAS pin, the first
charge pump immediately powers up.
2. If the BIAS voltage is 2.1V or higher, the IC comes out of
POR. Both SS and CT caps remain discharged and the
gate (GT) voltage remains low.
3. ENx
 pin, when pulled low (below its specified threshold),
enables the respective channel.
4. SSx cap begins to charge up through the internal 10礎
current source, the gate (GT) voltage begins to rise and
the corresponding output voltage begins to rise at the
same rate as the SS cap voltage. This is tightly controlled
by the soft-start amplifier shown in the block diagram.
5. SS cap begins to charge but the corresponding CTx cap
is held discharged.
6. Fault (FLT
) remains deasserted (stays high) and the
output voltage continues to rise.
7. If the load current on the output exceeds the set current
limit for greater than the OC timeout period, FLT
 gets
asserted and the channel shutdown occurs.
8. If the voltage on UV pin exceeds 633mV threshold as a
result of rising Vo, the Power Good (PG
) output goes
active.
9. At the end of the SS interval, the SS cap voltage reaches
CPVDD and remains charged as long as EN
 remains
asserted or there is no other fault condition present that
would attempt to pull down the gate.
State Diagram
This is shown in Figure 16. It provides a quick overview of
the IC operation and can also be used as a troubleshooting
road map.
ISL6173
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